The present invention relates generally to a liquid crystal display and a fabrication method thereof, and more particularly to a liquid crystal display having an overlaped structure that adjacent pixel electrodes with a dielectric interposed therebetween are overlapped each other.
Generally, color active matrix liquid crystal displays (AM-LCDs) with a fast response time, good display qualities, and a multiplicity of pixels, are expected to replace a the cathode ray tube. The AM-LCDs generally include an upper glass substrate, a lower glass substrate opposite the upper glass substrate, and liquid crystal layer interposed therebetween. On the lower glass substrate of these AM-LCDs are arranged a plurality of gate lines, a plurality of data lines crossed with the gate lines at right angle, and a plurality of switching elements such as thin film transistor or diode, each disposed in the vicinity of crossing points of the gate lines with the data lines. A plurality of pixel electrodes are also provided, each of which is connected with a corresponding one of the switching elements.
In most AM-LCDs, light transmittance is varied with alignment state of the liquid crystal molecules during the application of voltage to the pixel electrode. Therefore, images are displayed depending on the variation in the light transmittance. During the operation of AM-LCDs, so as to enhance the maintenance characteristic which maintain a voltage applied to the pixel electrode at a constant level, to stabilize gray scale, and to decrease flicker and residual image phenomena, storage capacitor is desirable for the AM-LCDs. For these purposes, storage on gate and storage on common modes were proposed and are both nowadays used. Storage on gate mode utilizes a portion of (n-1)-th gate line as an electrode for the storage capacitor corresponding to n-th pixel, while storage on common mode utilizes an additionally formed conductive line which is connected with the common electrode.
Proposed modes, however, cause drawbacks such as degeneration in aperture ratio, increase in delay time due to capacitance increase, and decrease in yield. In addition, they need an increase in operation capability of drive integrated circuit.
FIG. 1A is a partial plan view of a conventional liquid crystal display device and FIG. 1B is a sectional view taken along the line I-I' of FIG. 1A.
Here, numeral 1 is an insulating substrate, 2 a gate line formed on the insulating substrate, 2A a gate electrode extended from, and being one body with the gate line 2, and 2B a storage capacitor electrode. Also, numeral 3 is a gate insulating layer, 5 a data line, 5A a source electrode, 5B a drain electrode, 6 a passivation layer, and 7-1 and 7-2 pixel electrodes respectively.
First, referring to FIG. 1A, over the insulating substrate 1, there are disposed the gate and date lines 2 and 5 with perpendicular cross. So as to prevent the shorting between the two lines, an insulating layer(not shown) is disposed therebetween. In the vicinity of the intersections of the gate line 2 with the data line 5, there is a thin film transistor 10 including the gate electrode 2A which is extended from the gate line 2, the source electrode 5A which is extended from the data line 5, the drain electrode 5B spaced apart, opposite the source electrode 5A and a channel layer 4. Here, the gate and data lines 2 and 5 function not only the coherent role to scan addressing signals and transfer data signals but an additional one to define unit cell. The drain electrodes 5B are electrically connected to the transparent pixel electrodes 7-1, 7-2 of indium thin oxide(ITO). And, along the row direction, in parallel to the gate bus line 2, there is disposed a storage electrode 2B for the storage common mode described above.
FIG. 1B is a sectional view taken along the line I-I' of FIG. 1A.
Referring to FIG. 1B, on the insulating substrate 1, there is disposed an insulating layer 3 which is provided for insulation between the gate line 2 and the data line 5 of FIG. 1A. The data lines 5 made of an opaque metal film are disposed on the insulating layer 3. So as to protect the thin film transistor shown in FIG. 1A, a passivation layer 6 is formed on portions including the thin film transistor and the data line 5. Over the passivation layer 6, there are arranged the pixel electrodes 7-1, 7-2 of ITO to be overlapped with selected portions of the data line 5. Here, overlap of the pixel electrodes 7-1, 7-2 and the date line 5 is for increasing the overall storage capacitance in proportional to the overlapped area, thereby enhancing the display quality.
However, the additional electrode 2B for storage capacitor has a still drawback to decrease the aperture ratio because it is overlapped with each pixel electrode by a selected portion and does not pass the incident light thereto from the back light source. In addition, since adjacent pixel electrodes are closely disposed to each other to such a degree that the width therebetween reaches about 10 .mu.m, they may short to each other due to the fine pitch therebetween.